Recent years have seen a continued pattern of development in the computer field. In that regard, considerable effort has been directed to multiprocessors. Such systems involve a plurality of processors or function units capable of independent operation to process separate tasks in parallel. Usually, the tasks relate to a specified job.
Typically, a multiprocessor includes a plurality of computational units, a memory, a control and at least one input-output processor. Tasks of a job are initiated and processed, sometimes being moved from one computational unit to another. In the course of such operations, tasks must be synchronized and in that regard, a task may need data from another task or from the outside world, supplied through the input-output processor. Under such circumstances, there is a problem in timing and directing signals as well as determining interrupts. The situation is complicated when a task is in need of several signals to proceed with meaningful computation. Accommodating equitable priority among tasks further complicates operations.
Generally in computers, tasks are scheduled and executed in accordance with a scheme of priority. In relating such operations to multiprocessors, problems arise as tasks are shuttled about from processor to processor. To begin with, there is a problem of locating tasks. Accordingly, traditional synchronizing operations, as with respect to individual tasks in a multiprocessor, tend to be complex, time consuming and may be inequitable.
In multiprocessors, it has been previously proposed to provide an interrupt centralizer to maintain a record of the priorities for individual tasks. However, a need exists for a system with improved time economy. Specifically, the present invention recognizes the need for a system that identifies and locates the specific task that should see an interrupt and also determines the timing for interrupts as in relation to tasks awaiting individual signals. Accordingly, effective and time economical task scheduling is accomplished by systems of the present invention.
In general, the system of the present invention is associated in a multiprocessor in which individual tasks are initiated and executed. The system utilizes task status words (TSW) for readily determining the priority of each task, the current location of the task and the status of the task with respect to needed data as indicated by signals. Memory is provided for task status words, addressable on command to function in cooperation with a physical memory manager and an interrupt manager to schedule and synchronize individual tasks.
In an implementation of the system, structure is provided for assigning a task status word to each task when the task is initiated. Addressable memory contains the task status words which are maintained current and are available in relation to task activities. Accordingly, tasks may be effectively synchronized and coordinated on the basis of known task locations, signal significance, priorities and the status of signals relating to interrupts.